The present invention generally relates to compound semiconductor integrated circuits, and more particularly to a compound semiconductor integrated circuit such as a gallium arsenide (GaAs) integrated circuit having a built-in input interface circuit for converting an incoming logic signal of an emitter-coupled logic (ECL) level into a logic signal of a GaAs level which is used in an internal circuit which is provided at a stage subsequent to the interface circuit.
Recently, the integration density of GaAs integrated circuits has increased considerably, and thus, the GaAs integrated circuits are popularly used in applications where high speed operation and low power consumption are demanded. In such cases, there is a demand to use the GaAs integrated circuit together with the conventional ECL integrated circuit. Hence, an input interface circuit for converting the logic signal of the ECL level into the logic signal of the GaAs level is provided at the input part of the GaAs integrated circuit.
FIG. 1 shows an essential part of an example of a conventional GaAs integrated circuit having a built-in input interface circuit for converting an input logic signal of the ECL level into a logic signal of the GaAs level.
In FIG. 1, a logic signal SA having the ECL level, that is, a high level of -1.14 [V] and a low level of -1.52 [V], for example, is input to an input terminal 1. An input interface circuit 2 converts the logic signal SA of the ECL level into complementary logic signals SC and SC having the GaAs level, that is, a high level of -0.45 [V] and a low level of -1.25 [V], for example.
An internal circuit 3 is provided at a stage subsequent to the input interface circuit 2. This internal circuit 3 includes a positive phase input terminal 3A and an inverted phase input terminal 3B. An input part which is coupled to the positive and negative phase input terminals 3A and 3B has a threshold voltage of -0.8 [V] on the high level side and -0.9 [V] on the low level side, for example.
A power line 4 is set to a ground voltage GND, and a power line 5 supplies a power source voltage V.sub.SS1 which is lower than the ground voltage GND. For example, the power source voltage V.sub.SS1 is -1.25 [V]. In other words, the internal circuit 3 operates using the ground voltage GND as the power source voltage on the high voltage side, and using the power source voltage V.sub.SS1 as the power source voltage on the low voltage side.
In the input interface circuit 2, a differential amplifier circuit 6 forms an input buffer. Power lines 7 and 8 are set to the ground voltage GND. A power line 9 supplies a power source voltage VS.sub.SS2 which is lower than the power source voltage V.sub.SS1. For example, the power source voltage V.sub.SS2 is -2.0 [V].
It is of course possible to drive the internal circuit 3 by the same power source voltage V.sub.SS2 which is used to drive the input interface circuit 2. However, in order to reduce the power consumption and improve the operation speed of the internal circuit 3, the power source voltage V.sub.SS1 which is smaller in absolute value compared to the power source voltage V.sub.SS2 is used to drive the internal circuit 3. The power source voltages V.sub.SS1 and V.sub.SS2 are supplied from independent power sources.
Enhancement type Schottky gate field effect transistors (hereinafter simply referred to as E-FETs) 10 and 11 are provided as driving transistors. A reference voltage V.sub.ref is applied to a reference voltage input terminal 12 and is supplied to E-FET 11. For example, the reference voltage V.sub.ref is -1.33 [V].
On the other hand, a depletion type Schottky gate field effect transistor (hereinafter simply referred to as D-FET) 13 forms a current source. The D-FETs 14 and 15 are used as loads.
The circuit constants of the differential amplifier circuit 6 are set so that the high level threshold voltage is -0.9 [V] and the low level threshold voltage is -1.9 [V], for example, and outputs a positive phase logic signal SB via a node 16 and an inverted phase logic signal SB via a node 17. For example, the positive and inverted phase logic signals SB and SB have a high level of 0 [V] and a low level of -1.0 [V].
In the input interface circuit 2, a level conversion circuit 18 converts the positive phase logic signal SB output from the differential amplifier circuit 6 into the positive phase logic signal SC having the GaAs level. This level conversion circuit 18 includes an E-FET 21 connected to a power line 19 which is set to the ground voltage GND, a diode 22, and a D-FET 23 connected to a power line 20 which supplies the power source voltage V.sub.SS2. The positive phase logic signal SC of the GaAs level is output via a node 24.
The circuit constants of the level conversion circuit 18 are set so that the level conversion circuit 18 outputs -0.45 [V], for example, which is the high level of the GaAs level when the E-FET 21 is ON and outputs -1.25 [V], for example, which is the low level of the GaAs level when the E-FET 21 is OFF.
In addition, in the input interface circuit 2, a level conversion circuit 25 converts the inverted phase logic signal SB which is output from the differential amplifier circuit 6 into the inverted phase logic signal SC of the GaAs level. This level conversion circuit 25 includes an E-FET 28 connected to a power line 26 which is set to the ground voltage GND, a diode 29, and a D-FET 30 which is connected to a power line 27 which supplies the power source voltage V.sub.SS2. The inverted phase logic signal SC of the GaAs level is output via a node 31.
The circuit constants of the level conversion circuit 25 are set so that the level conversion circuit 25 outputs -0.45 [V], for example, which is the high level of the GaAs level when the E-FET 28 is ON and outputs -1.25 [V], for example, which is the low level of the GaAs level when the E-FET 28 is OFF.
In the GaAs integrated circuit described above, if the logic signal SA of the ECL level input to the input terminal 1 has the high level, the E-FET 10 of the differential amplifier circuit 6 turns ON and the E-FET 11 of the differential amplifier circuit 6 turns OFF. Hence, the positive and negative phase signals SB and SB output from the differential amplifier circuit 6 respectively have the high level and the low level.
As a result, the E-FET 21 of the level conversion circuit 18 turns ON, and a signal having the high level of the GaAs level is output via the node 24. This signal output via the node 24 is supplied to the positive phase input terminal 3A of the internal circuit 3. On the other hand, the E-FET 28 of the level conversion circuit 25 turns OFF, and a signal having the low level of the GaAs level is output via the node 31. This signal output via the node 31 is supplied to the inverted phase input terminal 3B of the internal circuit 3.
On the other hand, if the logic signal SA of the ECL level input to the input terminal 1 has the low level, the E-FETs 10 and 11 of the differential amplifier circuit 6 respectively turn OFF and ON. Hence, the positive phase logic signal SB and the inverted phase logic signal SB output from the differential amplifier circuit 6 respectively have the low level and the high level.
As a result, the E-FET 21 of the level conversion circuit 18 turns OFF, and a signal having the low level of the GaAs level is output via the node 31. This signal output via the node 31 is supplied to the inverted phase input terminal 3B of the internal circuit 3.
In the conventional GaAs integrated circuit, the input interface circuit 2 and the internal circuit 3 use mutually different power source voltages on the low voltage side. For this reason, if the power source voltage V.sub.SS1 undergoes an absolute or relative deviation with respect to the power source voltage V.sub.SS2, the threshold voltages of the input part of the internal circuit 3 undergo an absolute or relative deviation with respect to the logic signals SC and SC which are output from the interface circuit 2. If the threshold voltages of the input part of the internal circuit 3 undergo an absolute or relative deviation with respect to the logic signals SC and SC, the logic signals SC and SC output from the input interface circuit 2 cannot be transferred correctly to the internal circuit 3, and there is a problem in that an erroneous operation is generated.
FIG. 2 is a diagram for explaining the deviation of the threshold voltages of the input part of the internal circuit 3. In FIG. 2(a) shows the high level and the low level of the logic signals SC and SC which are output from the input interface circuit 2, where VOH and VOL respectively denote the high level and the low level.
On the other hand, FIG. 2(b) shows the threshold voltages of the input part of the internal circuit 3 for the case where the power source voltage V.sub.SS1 undergoes no absolute or relative deviation with respect to the power source voltage V.sub.SS2, where VIH and VIL respectively denote the high level and the low level of the threshold voltages. In this case, VOH&gt;VIH and VOL&lt;VIL. Hence, the input part of the internal circuit 3 can accurately judge the high and low levels of the signals output from the input interface circuit 2.
In FIG. 2(c) shows an example of a deviation in the threshold voltages of the input part of the internal circuit 3 for the case where the power source voltage V.sub.SS1 undergoes an absolute or relative deviation in the negative direction with respect to the power source voltage V.sub.SS2, where VIH' and VIL' respectively denote the threshold voltages for the high level and the low level. Since VOL&gt;VIL' in this case, the input part of the internal circuit 3 cannot judge the low level of the signals which are output from the input interface circuit 2.
In addition, in FIG. 2(d) shows an example of a deviation in the threshold voltages of the input part of the internal circuit 3 for the case where the power source voltage V.sub.SS1 undergoes an absolute or relative deviation in the positive direction with respect to the power source voltage V.sub.SS2, where VIH" and VIL" respectively denote the threshold voltages for the high level and the low level. Since VOH&lt;VIH" in this case, the input part of the internal circuit 3 cannot judge the high level of the signals which are output from the input interface circuit 2.